1. Field of the Invention
This invention relates to a method of forming contact holes or through holes in a semiconductor integrated circuit device, and more particularly, to improvement of the degree of the step coverage of a wiring metal layer.
2. Description of the Related Art
As is represented by VLSI, for example, recent semiconductor integrated circuit devices have been considerably improved in their function and integration density. As a result of this, the technology of forming fine patterns becomes more important. Further, a multi-layered wiring is required in order to improve the function and the integration density of the semiconductor integrated circuit device. In this case, layer-insulation films are formed between respective wiring layers of the multi-layered wiring. The wiring layers are electrically connected to each other by means of through holes selectively formed in the layer-insulation films.
An isotropic etching method is generally used to form the through holes. Further, in recent years, an anisotropic etching method has also been used. A reactive ion etching (RIE) method is known as one of the anisotropic etching methods. The RIE method has superior characteristics that the amount of etching in a lateral direction is small in the etching process and the amount of etching can be easily controlled. Therefore, the through holes can be formed with a precise and small size by use of the RIE method in comparison with the case of using the isotropic etching method. Therefore, the RIE method is generally used to form through holes and contact holes (which are hereinafter referred to simply as holes) in the semiconductor integrated circuit device with a high integration density.
In the case where the holes are formed by the RIE method, the side walls of the holes make an angle substantially equal to right angles with respect to the semiconductor substrate. Therefore, when a metal wiring layer is formed on the layer-insulation film and in the holes by a sputtering method, the metal wiring layer becomes thin on the side wall section in comparison with other sections by the shadowing effect, and it tends to be cut off at the stepped portion. Further, the metal wiring layer may be cut off by the electromigration which is caused by concentration of an operation current generated during the operation of the semiconductor integrated circuit device.
In order to enhance the step coverage of the metal wiring layer and prevent the cut-off of the metal wiring layer at the stepped portion, the side wall of the hole is tapered. To obtain the tapered hole, a photoresist pattern is etched in a lateral direction or the exposed edge portion thereof is etched by the RIE method. That is, the side wall of the hole is tapered by gradually enlarging the pattern opening by the RIE method. In order to etch the photoresist pattern in a lateral direction, it is necessary to set the etching rates of the layer-insulation film and the photoresist substantially equal each other. By setting the etching rates of the layer-insulation film and the photoresist substantially equal to each other, the edge portion of the photoresist pattern is etched more as it becomes thinner in the etching process. Thus, when the edge portion of the photoresist film is gradually etched in a lateral direction in the etching process, the side wall of the hole can be tapered. In this case, if it is required to form a sharply tapered hole, a thick photoresist film is formed. However, if the photoresist film is formed thick, variation in the size of the hole becomes large, preventing formation of small holes. The above variation in the size of the hole becomes significant when the thickness of the photoresist film is larger than 1 .mu. m. In the case of using a photoresist film with a thickness of less than 1 .mu.m, the tapering angle of the side wall of the hole becomes small and it becomes difficult to sufficiently suppress reduction in the thickness of the metal wiring layer on the side wall portion which is caused by the shadowing effect. Further, the photoresist film may become rapidly thin as the etching process advances. As a result the possibility arises that pin-holes may be formed in the thin portion of the photoresist film. With the pinholes formed in the photoresist film, a corresponding portion of the layer-insulation film is etched. In this case, it is impossible to attain sufficient insulation between conductive layers formed on the upper and lower sides of the layer-insulation film.
In order to overcome the defects caused by using the RIE method as described above, a combination of the RIE method and isotropic etching method is used as the hole formation method. In this method, the isotropic etching method is first effected to etch that part of the layer-insulation film in which the hole is to be formed. In this way, a recess is formed in the layer-insulation film by the isotropic etching process. Next, a hole is formed in the layer-insulation film within the recess by the RIE method. The hole has a diameter smaller than the recess and is formed to reach the wiring layer formed under the layer-insulation film. This combination of the hole and recess is used as a through hole. That is, the through hole is formed to have a tapered opening which is provided by the recess formed by the isotropic etching method. Since the side wall of the through hole normal to the semiconductor substrate becomes short, the metal wiring layer formed on the layer-insulation film in a position corresponding to the through hole is prevented from being thin at more portion of the through hole, enhancing the step coverage of the metal wiring layer.
However, the through hole of the structure formed by the RIE method as described above still has a side wall portion which is normal to the semiconductor substrate. Therefore, even though the step coverage of the wiring layer on the stepped portion can be improved to some extent, the step coverage of the wiring layer on the side wall cannot be significantly improved. Thus, a satisfactory step coverage cannot be attained.
Another conventional forming method has been proposed in which the hole formed in the layer-insulation film is filled with polysilicon. In this case, a metal wiring layer is formed on the polysilicon layer and the layer-insulation film. Since the metal wiring layer is formed on the flat portion, the step coverage can be significantly improved. However, in this case, the manufacturing process becomes considerably complicated.